Improving Hardware Branch Predictors using Artificial Neural Networks

An abstract of the thesis of Andres Anibal Rustan for the Masters of Science in Electrical and Computer Engineering were presented November 1, 1999. Title: Improving Hardware Branch Predictors using Artificial Neural Networks This research shows that using an Artificial Neural Network as the hardware branch predictor of a microprocessor leads to performance as good as standard branch predictors for comparable chip area. The results were obtained running several Spec95 benchmarks on an augmented version of the simplescalar architecture simulator. The approach taken in this research is the first attempt to use Neural Networks to improve the design of hardware branch predictors, it points to a combination of static and dynamic techniques using artificial intelligence. The prediction rates achieved by the holistic-non-adaptive Neural Network predictor designed are promising. Even a simple Neural Network structure without an on-line adaptive mechanism performed better than current techniques for small predictor sizes. The neural net predictor achieved almost the same rates for most of the benchmarks of the Spec95 set and it was even 20% more accurate for one of them. However, the NN predictors developed were not able to achieve the same prediction rates than bigger standard predictor configurations. The performance of the non-adaptive NN predictors substantially decreases when the number of dynamic branches in the benchmark increases, showing that the dynamic characteristic of the benchmarks negatively affects the behavior of the non-adaptive Neural Network predictor. This indicates that in order to increase the prediction rate in highly dynamic programs it would be necessary to incorporate an adaptive mechanism, to yield Neural Network predictors competitive with the larger standard configurations. The method used was to train an Artificial Neural Network on the dynamics of programs, and particularly conditional branch instructions, when they are being executed in a microprocessor. After training the Neural Network on traces of programs, it was implemented in the simulator to replace the existent standard predictor with comparable results. Improving Hardware Branch Predictors using Artificial Neural Networks Submitted by Andres A. Rustan For Partial Fulfillment of Masters of Science in Electrical and Computer Engineering Department of Electrical Engineering Portland State University Portland, Oregon USA November, 1999